1. Field of the Invention
The present invention relates to passive components fabricated on a semiconductor integrated circuit die, and more particularly, to inductors and transformers fabricated on the integrated circuit die and comprising a plurality of conductive layers having insulation layers interleaved therebetween.
2. Description of the Related Technology
Analog electronic circuits, especially those operating at radio frequency, may include inductors and transformers for filtering, frequency mixing, oscillators, interstage radio frequency coupling, and high frequency pulse coupling. Transformers are adapted to pass alternating current (AC) signals and block direct current (DC). Inductors and transformers have been fabricated in many forms, from large iron core transformers used at power frequencies to air core inductors used at radio frequencies. Radio frequency inductors and transformers have been enclosed in metal cans, non-conductive coil forms, open construction, fabricated onto a printed circuit board and the like. More recently with the advent of integrated circuits and electronic miniaturization the need arose to reduce the size of external discrete components necessary with an integrated circuit product, preferably, elimination of any discrete components was a primary goal. More and more formerly discrete components were fabricated onto integrated circuits, i.e., resistors, capacitors and inductors, for both size and cost reasons. Inductors were especially a problem because the physical size and geometry normally required for an effective inductor over a desired range of frequencies.
An inductor fabricated on an integrated circuit substrate generally has been formed in the shape of a spiral coil structure in a single metal layer on an insulation layer using typical integrated circuit fabrication techniques. This spiral coil structure requires a substantial area of the silicon integrated circuit substrate, typically for example, 200 xcexcmxc3x97200 xcexcm. The spiral coil structure also suffers from parasitic capacitive influence from the integrated circuit substrate on which it is fabricated. Fabrication on an integrated circuit substrate of an efficient transformer (two inductors electromagnetically coupled together) is also extremely difficult using spiral coil structure shapes because of the physical size required and the inherent parasitic capacitance which may render the resulting transformer structure inefficient or ineffective for a desired purpose.
What is needed are more effective and efficient inductor and transformer structures that may be easily and inexpensively fabricated on an integrated circuit substrate and do not have to occupy a substantial area of the substrate.
The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing on a monolithic semiconductor integrated circuit die an inductor comprising a plurality of conductive layers shaped into coil turns and interleaved with a plurality of insulation layers. The conductive layer coil turns are stacked vertically (perpendicular to the horizontal plane of the conductive coil layers) and proximate to one another so as to achieve close magnetic coupling therebetween, thereby achieving a larger inductance value for a given sized coil structure. The conductive layer coil turns are connected together with conductive vias through the interposing insulation layers. It is contemplated and within the scope of the present invention that the conductive layer coil turns may be of any shape, such as for example but not limitation, round, square, triangular, oval, hexagonal and the like.
According to an embodiment of the invention, a transformer may be fabricated in a similar fashion by having concentric or co-axial inductors formed from the plurality of conductive coil layers with a plurality of insulation layers interleaved therebetween. The vertically stacked conductive coil layers of each of the individual inductors of the transformer are connected together with conductive vias through the interposing insulation layers. The conductive vias may include a plurality of vias connecting adjacent conductive coil layers so as to keep series resistance low in the connection thereof. The conductive layers (coil turns) and vias may be made from metal such as copper, aluminum, alloys and the like; doped polysilicon, or any other type of conductive material that may be used in the fabrication of circuits and connections on an integrated circuit substrate.
In an embodiment of the present invention, fabricated on a monolithic semiconductor integrated circuit die is a plurality of conductive layers with a plurality of insulation layers therebetween. The conductive and insulation layers are interleaved one with the other. Each of the plurality of coil turn conductive layers has substantially the same diameter and an insulation layer is interposed between two adjacent coil turn conductive layers. The insulation layer is only as thick as required, resulting in the adjacent coil turn conductive layers having increased magnetic coupling and reduced parasitic capacitance with the substrate. In addition, the adjacent closely spaced and vertically stacked coil turns have substantially the same voltage potential thereon so that capacitive coupling therebetween is minimized. Only one coil turn is adjacent to the integrated circuit substrate and has a relatively small footprint. This greatly reduces parasitic capacitance from the substrate. Conductive Vias are formed in the insulation layers between adjacent coil turns of the conductive layers and connect the end points (open portions) of the adjacent coil turns together.
In another embodiment of the present invention, the plurality of conductive layers having a plurality of insulation layers therebetween are arranged as two inductor coils. The two coils are concentric, one of the inductor coils located within the other one and coaxially aligned therein. Each conductive layer comprises a coil turn for each of the two inductor coils. The conductive and insulation layers are interleaved one with the other. The one (first) of the two inductor coils has a larger inside diameter then the outside diameter of the other one (second) of the two coils, wherein the second inductor coil fits inside of the first inductor coil and is concentric therewith. It is contemplated and within the scope of the present invention that the first and second inductor coils have the same number of turns (same number of layers) or a different number of turns (some of the conductive layers not used by one or the other of the two inductor coils). Thus impedance matching and/or voltage step-up or step-down between the input and output of the transformer may be readily achieved with this embodiment of the invention. The adjacent coil turn conductive layers have increased magnetic coupling therebetween and reduced parasitic capacitance with the substrate. In addition, the adjacent closely spaced and vertically stacked coil turns have substantially the same voltage potential thereon so that capacitive coupling therebetween is minimized. Only one coil turn of each of the two inductor coils is adjacent to the integrated circuit substrate and has a relatively small footprint. This greatly reduces parasitic capacitance from the substrate to the transformer. Conductive Vias are formed the insulation layers between adjacent coil turns of the conductive layers and connect the end points (open portions) of the adjacent coil turns together.
According to the aforementioned embodiments of the present invention, the insulation layers between the coil turns of the inductor(s) may preferably be very thin so that the adjacent turns of the coil are close together, thus, improving the magnetic coupling therebetween and increasing the effective inductance for a given size coil diameter. It is also contemplated and within the scope of the present invention that a material of high magnetic permeability may be used by locating same within the coil so as to further increase the effective inductance value for a give size of coil structure. This material may be, for example but not limitation: iron, iron oxide, ferrite ceramic, ferrous oxide or other materials that increase the effective inductance value of the inductor coil and transformer.
An advantage of the present invention is that the inductor/transformer structure occupies less area of the integrated circuit substrate.
Another advantage is that parasitic capacitance of the integrated circuit substrate is reduced.
Still another advantage is mutual inductance or inductive coupling between the two coils of the transformer is enhance because of the close proximity of the two coils.
A feature of the present invention is fabricating a coil inductor on a semiconductor integrated circuit die by depositing each conductive layer turn of the coil on a respective insulation layer and connecting the turns together with conductive vias through these respective insulation layers.
Yet another feature is using a plurality of vias between adjacent conductive layer turns to reduce the connection resistance therebetween.
Another feature is positioning a second coil concentrically inside of a first coil on an integrated circuit substrate so that both of the first and second coils are in coaxial alignment and electromagnetically coupled together to form a transformer.
Still another feature is impedance matching with a transformer fabricated on the integrated circuit substrate.
Another feature is placing a magnetic material within the coil fabricated on the integrated circuit substrate for increasing the inductance thereof.
Yet another feature is AC voltage step-up and step-down with a transformer fabricated on the integrated circuit substrate.
Other and further features and advantages will be apparent from the following description of presently preferred embodiments of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.